1. 17 Jun, 2013 3 commits
    • Jonathan Austin's avatar
      ARM: mpu: Ensure that MPU depends on CPU_V7 · de829776
      Jonathan Austin authored
      The support for the MPU is currently implemented only for R-class
      (PMSAv7/R). Since the merge of V7M support in to the kernel it is possible
      to select MPU support on V7M.
      This patch ensures that until MPU support for M-class processors is
      implemented, the MPU can only be selected with R-class CPUs
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Acked-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
    • Jonathan Austin's avatar
      ARM: mpu: protect the vectors page with an MPU region · 9dfc28b6
      Jonathan Austin authored
      Without an MMU it is possible for userspace programs to start executing code
      in places that they have no business executing. The MPU allows some level of
      protection against this.
      This patch protects the vectors page from access by userspace processes.
      Userspace tasks that dereference a null pointer are already protected by an
      svc at 0x0 that kills them. However when tasks use an offset from a null
      pointer (eg a function in a null struct) they miss this carefully placed svc
      and enter the exception vectors in user mode, ending up in the kernel.
      This patch causes programs that do this to receive a SEGV instead of happily
      entering the kernel in user-mode, and hence avoid a 'Bad Mode' panic.
      As part of this change it is necessary to make sigreturn happen via the
      stack when there is not an sa_restorer function. This change is invisible to
      userspace, and irrelevant to code compiled using a uClibc toolchain, which
      always uses an sa_restorer function.
      Because we don't get to remap the vectors in !MMU kuser_helpers are not
      in a defined location, and hence aren't usable. This means we don't need to
      worry about keeping them accessible from PL0
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Nicolas Pitre <nico@linaro.org>
      CC: Catalin Marinas <catalin.marinas@arm.com>
    • Jonathan Austin's avatar
      ARM: mpu: Allow enabling of the MPU via kconfig · 801bb21c
      Jonathan Austin authored
      Allows the user to select MPU support when compiling for ARM processors
      that support the PMSAv7.
      This ensures that CONFIG_SMP depends on the MPU in the case that no MMU
      is present.
      CONFIG_SMP_ON_UP is not implemented for nommu, so introduce an MMU
      dependency there.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
  2. 07 Jun, 2013 16 commits
    • Jonathan Austin's avatar
      ARM: mpu: add MPU initialisation for secondary cores · eb08375e
      Jonathan Austin authored
      The MPU initialisation on the primary core is performed in two stages, one
      minimal stage to ensure the CPU can boot and a second one after
      sanity_check_meminfo. As the memory configuration is known by the time we
      boot secondary cores only a single step is necessary, provided the values
      for DRSR are passed to secondaries.
      This patch implements this arrangement. The configuration generated for the
      MPU regions is made available to the secondary core, which can then use the
      asm MPU intialisation code to program a complete region configuration.
      This is necessary for SMP configurations without an MMU, as the MPU
      initialisation is the only way to ensure that memory is specified as
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Nicolas Pitre <nico@linaro.org>
    • Jonathan Austin's avatar
      ARM: mpu: Complete initialisation of the MPU after reaching the C-world · 9a271567
      Jonathan Austin authored
      Much like with the MMU, MPU initialisation is performed in two stages; the
      first in the pre-C world and the 'real' initialisation during arch setup.
      This patch wires in previously added MPU initialisation functions so that
      the whole of memory is mapped with the appropriate region properties for
      'normal' RAM (the appropriate properties depend on whether the system is
      Stub initialisation functions are added for the case that there MPU support
      is not configured in to the kernel.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Hyok S. Choi <hyok.choi@samsung.com>
    • Jonathan Austin's avatar
      ARM: mpu: add MPU probe and initialisation functions in C · 5ad7dcbe
      Jonathan Austin authored
      This patch adds new functions for probing and initialising the ARMv7
      PMSA-compliant MPU.
      These use the pre-defined and reserved MPU_PROBE_REGION for establishing
      properties of the MPU, which is necessary because certain probe operations
      require modifying region properties and reading back the results.
      This patch also introduces a minimal sanity_check_meminfo_mpu function, that
      ensures that the memory set-up passed to the kernel can be used in conjunction
      with the MPU. The base address of a region must be aligned to the region size,
      otherwise behavior is unpredictable and region sizes can only be specified as a
      power-of-two. To simplify the satisfaction of these requirements this
      implementation currently enforces that all memory is contiguous from
      PHYS_OFFSET, merging banks that are contiguous but passed in separately.
      The functions are added in this patch but wired in to the boot process later
      in the series.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Hyok S. Choi <hyok.choi@samsung.com>
    • Jonathan Austin's avatar
      ARM: mpu: add early bring-up code for the ARMv7 PMSA-compliant MPU · 67c9845b
      Jonathan Austin authored
      This patch adds initial support for using the MPU, which is necessary for
      SMP operation on PMSAv7 processors because it is the only way to ensure
      memory is shared. This is an initial patch and full SMP support is added
      later in this series.
      The setup of the MPU is performed in a way analagous to that for the MMU:
      Very early initialisation before the C environment is brought up, followed
      by a sanity check and more complete initialisation in C.
      This patch provides the simplest possible memory region configuration:
      MPU_PROBE_REGION: Reserved for probing MPU details, not enabled
      MPU_BG_REGION: A 'background' region that specifies all memory strongly ordered
      MPU_RAM_REGION: A single shared, cacheable, normal region for the valid RAM.
      In this early initialisation code we simply map the whole of the address
      space with the BG_REGION and (at least) the kernel with the RAM_REGION. The
      MPU has region alignment constraints that require us to round past the end
      of the kernel.
      As region 2 has a higher priority than region 1, it overrides the strongly-
      ordered behaviour for RAM only.
      Subsequent patches will add more complete initialisation from the C-world
      and support for bringing up secondary CPUs.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Hyok S. Choi <hyok.choi@samsung.com>
    • Jonathan Austin's avatar
      ARM: mpu: add header for MPU register layouts and region data · a2b45b0d
      Jonathan Austin authored
      This commit adds definitions relevant to the ARM v7 PMSA compliant MPU.
      The register layouts and region configuration data is made accessible to asm
      as well as C-code so that it can be used in early bring-up of the MPU.
      The mpu region information structs assume that the properties for the I/D side
      are the same, though the implementation could be trivially extended for future
      platforms where this is no-longer true.
      The MPU_*_REGION defines are used for the basic, static MPU region setup.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
    • Jonathan Austin's avatar
      ARM: mpu: add PMSA related registers and bitfields to existing headers · aca7e592
      Jonathan Austin authored
      This patch adds the following definitions relevant to the PMSA:
      Add SCTLR bit 17, (CR_BR - Background Region bit) to the list of CR_*
      bitfields. This bit determines whether to use the architecturally defined
      memory map
      Add the MPUIR to the available registers when using read_cpuid macro. The
      MPUIR is the MPU type register.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      CC:"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
    • Jonathan Austin's avatar
      ARM: vexpress: Add Cortex-R Series UART, selectable via DEBUG_LL · ed18bdc8
      Jonathan Austin authored
      The Cortex-R series processors on Versatile Express have a different memory
      map to the RS1 and CA9X4 tiles. Most of the platform difference can be
      expressed in device-trees, but the UART definitions for LL_DEBUG cannot.
      This patch defines the UART location for R-Series processors on
      versatile-express, allowing low-level debug and output from the decompressor.
      These definitions are selectable via Kconfig
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      CC: Pawel Moll <pawel.moll@arm.com>
    • Jonathan Austin's avatar
      ARM: add Cortex-R7 Processor Info · c90ad5c9
      Jonathan Austin authored
      This patch adds processor info for ARM Ltd. Cortex-R7.
      The R7 has many similarities to the A9 and though the ACTLR layout is not
      identical, the bits associated with cache operations broadcasting and SMP
      modes are the same for A9, A5 and R7 (Though in the A-class processors the
      same bits toggle TLB-ops broadcasting as well as cache-ops)
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Catalin Marinas <catalin.marinas@arm.com>
      CC: Stephen Boyd <sboyd@codeaurora.org>
    • Jonathan Austin's avatar
      ARM: select CPU_CPU15_MMU/MPU appropriately · 66567618
      Jonathan Austin authored
      Currently CPU_V7 selects CPU_CP15_MMU, however in the case of a V7 CPU
      implementing the PMSA, such as the Cortex-R7, the CP15_MMU operations are
      not available. Selecting CPU_CP15_MPU is appropriate in this case.
      This patch makes CPU_CP15_MMU dependent on the use of the MMU, selecting
      CPU_CP15_MPU for v7 processors when !MMU is chosen.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
    • Jonathan Austin's avatar
      ARM: nommu: add stub local_flush_bp_all() for !CONFIG_MMUU · 8d655d83
      Jonathan Austin authored
      Since the merging of Will's tlb-ops branch, specifically 89c7e4b8
      (ARM: 7661/1: mm: perform explicit branch predictor maintenance when required),
      building SMP without CONFIG_MMU has been broken.
      The local_flush_bp_all function is only called for operations related to
      changing the kernel's view of memory and ASID rollover - both of which are
      irrelevant to an !MMU kernel.
      This patch adds a stub local_flush_bp_all() function to the other tlb
      maintenance stubs and restores the ability to build an SMP !MMU kernel.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
    • Jonathan Austin's avatar
      ARM: nommu: Don't build smp_tlb.c for !CONFIG_MMU · 8006b4d1
      Jonathan Austin authored
      Without an MMU we don't need to do any TLB maintenance. Until the addition
      of 93dc6887 (ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181
      (TLBI/DSB operations)) building the tlb maintenance ops in smp_tlb.c worked,
      though none of the contents were used.
      Since that commit, however, SMP NOMMU has not been able to build. This patch
      restores that ability by making the building of smp_tlb.c dependent on MMU.
      Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      Acked-by: Catalin Marinas's avatarCatalin Marinas <catalin.marinas@arm.com>
      CC: Will Deacon <will.deacon@arm.com>
    • Will Deacon's avatar
      ARM: suspend: fix CPU suspend code for !CONFIG_MMU configurations · aa1aadc3
      Will Deacon authored
      The ARM CPU suspend code can be selected even for a !CONFIG_MMU
      configuration. The resulting kernel will not compile and, even if it did,
      would access undefined co-processor registers when executing.
      This patch fixes the v6 and v7 CPU suspend code for the nommu case.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Tested-by: default avatarJonathan Austin <jonathan.austin@arm.com>
      CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> (commit_signer:1/3=33%)
      CC: Santosh Shilimkar <santosh.shilimkar@ti.com> (commit_signer:1/3=33%)
      CC: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
    • Will Deacon's avatar
      ARM: nommu: do not initialise page tables in secondary_data structure · c4a1f032
      Will Deacon authored
      nommu systems do not require any page tables, so don't try to initialise
      them when bringing up secondary cores.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Will Deacon's avatar
      ARM: nommu: provide dummy cpu_switch_mm implementation · 02ed1c7b
      Will Deacon authored
      cpu_switch_mm is a logical nop on nommu systems, so define it as such
      when !CONFIG_MMU.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Will Deacon's avatar
      ARM: nommu: define dummy TLB operations for nommu configurations · 5c709e69
      Will Deacon authored
      nommu platforms do not perform address translation and therefore clearly
      don't have TLBs. However, some SMP code assumes the presence of the TLB
      flushing routines and will therefore fail to compile for a nommu system.
      This patch defines dummy local_* TLB operations and #defines
      tlb_ops_need_broadcast() as 0, therefore causing the usual ARM SMP TLB
      operations to call the local variants instead.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      CC: Nicolas Pitre <nico@linaro.org>
    • Will Deacon's avatar
      ARM: nommu: add entry point for secondary CPUs to head-nommu.S · 01fafcab
      Will Deacon authored
      This patch adds a secondary_startup entry point to head-nommu.S so that
      we can boot secondary CPUs on an SMP nommu configuration.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
      CC: Nicolas Pitre <nico@linaro.org>
  3. 22 May, 2013 2 commits
    • Russell King's avatar
      Merge tag '3.10-rc2-psci-ops-11-tag' of... · 78ecad01
      Russell King authored
      Merge tag '3.10-rc2-psci-ops-11-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen into devel-stable
      Pull psci_smp_ops support from Stefano Stabellini:
      It contains the generic PSCI patch and the smp_init patch that we
      discussed so much about.  I think it would be helpful for other
      people if you could create a stable branch with these patches so
      that SoC devs can base their work on it.
    • Russell King's avatar
      Merge branch 'for-next' of git://git.pengutronix.de/git/ukl/linux into devel-stable · f150abe1
      Russell King authored
      Pull ARM-v7M support from Uwe Kleine-König:
      "All but the last patch were in next since next-20130418 without issues.
      The last patch fixes a problem in combination with
        8164f7af (ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register)
      which triggers a WARN_ON without an implemented read_cpuid_ext.
      The branch merges fine into v3.10-rc1 and I'd be happy if you pulled it
      for 3.11-rc1. The only missing piece to be able to run a Cortex-M3 is
      the irqchip driver that will go in via Thomas Gleixner and platform
      specific stuff."
  4. 21 May, 2013 9 commits
    • Linus Torvalds's avatar
      Merge branch 'leds-fixes-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds · 519fe2ec
      Linus Torvalds authored
      Pull LED subsystem fix from Bryan Wu.
      * 'leds-fixes-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds:
        leds: leds-gpio: reserve gpio before using it
    • Timo Teräs's avatar
      leds: leds-gpio: reserve gpio before using it · 803d19d5
      Timo Teräs authored
      This reverts commit a99d76f9 (leds: leds-gpio: use gpio_request_one)
      and commit 2d7c22f6 (leds: leds-gpio: set devm_gpio_request_one()
      flags param correctly) which was a fix of the first one.
      The conversion to devm_gpio_request in commit e3b1d44c (leds:
      leds-gpio: use devm_gpio_request_one) is not reverted.
      The problem is that gpio_cansleep() and gpio_get_value_cansleep()
      calls can crash if the gpio is not first reserved. Incidentally this
      same bug existed earlier and was fixed similarly in commit d95cbe61
      (leds: Fix potential leds-gpio oops). But the OOPS is real. It happens
      when GPIOs are provided by module which is not yet loaded.
      So this fixes the following BUG during my ALIX boot (3.9.2-vanilla):
      BUG: unable to handle kernel NULL pointer dereference at 0000004c
      IP: [<c11287d6>] __gpio_cansleep+0xe/0x1a
      *pde = 00000000
      Oops: 0000 [#1] SMP
      Modules linked in: leds_gpio(+) via_rhine mii cs5535_mfd mfd_core
      geode_rng rng_core geode_aes isofs nls_utf8 nls_cp437 vfat fat
      ata_generic pata_amd pata_cs5536 pata_acpi libata ehci_pci ehci_hcd
      ohci_hcd usb_storage usbcore usb_common sd_mod scsi_mod squashfs loop
      Pid: 881, comm: modprobe Not tainted 3.9.2 #1-Alpine
      EIP: 0060:[<c11287d6>] EFLAGS: 00010282 CPU: 0
      EIP is at __gpio_cansleep+0xe/0x1a
      EAX: 00000000 EBX: cf364018 ECX: c132b8b9 EDX: 00000000
      ESI: c13993a4 EDI: c1399370 EBP: cded9dbc ESP: cded9dbc
       DS: 007b ES: 007b FS: 00d8 GS: 0033 SS: 0068
      CR0: 8005003b CR2: 0000004c CR3: 0f0c4000 CR4: 00000090
      DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
      DR6: ffff0ff0 DR7: 00000400
      Process modprobe (pid: 881, ti=cded8000 task=cf094aa0 task.ti=cded8000)
       cded9de0 d09471cb 00000000 c1399260 cf364014 00000000 c1399260 c1399254
       d0949014 cded9df4 c118cd59 c1399260 d0949014 d0949014 cded9e08 c118ba47
       c1399260 d0949014 c1399294 cded9e1c c118bb75 cded9e24 d0949014 00000000
      Call Trace:
       [<d09471cb>] gpio_led_probe+0xba/0x203 [leds_gpio]
       [<c118cd59>] platform_drv_probe+0x26/0x48
       [<c118ba47>] driver_probe_device+0x75/0x15c
       [<c118bb75>] __driver_attach+0x47/0x63
       [<c118a727>] bus_for_each_dev+0x3c/0x66
       [<c118b6f9>] driver_attach+0x14/0x16
       [<c118bb2e>] ? driver_probe_device+0x15c/0x15c
       [<c118b3d5>] bus_add_driver+0xbd/0x1bc
       [<d08b4000>] ? 0xd08b3fff
       [<d08b4000>] ? 0xd08b3fff
       [<c118bffc>] driver_register+0x74/0xec
       [<d08b4000>] ? 0xd08b3fff
       [<c118c8e8>] platform_driver_register+0x38/0x3a
       [<d08b400d>] gpio_led_driver_init+0xd/0x1000 [leds_gpio]
       [<c100116c>] do_one_initcall+0x6b/0x10f
       [<d08b4000>] ? 0xd08b3fff
       [<c105e918>] load_module+0x1631/0x1907
       [<c10975d6>] ? insert_vmalloc_vmlist+0x14/0x43
       [<c1098d5b>] ? __vmalloc_node_range+0x13e/0x15f
       [<c105ec50>] sys_init_module+0x62/0x77
       [<c1257888>] syscall_call+0x7/0xb
      EIP: [<c11287d6>] __gpio_cansleep+0xe/0x1a SS:ESP 0068:cded9dbc
      CR2: 000000000000004c
       ---[ end trace 5308fb20d2514822 ]---
      Signed-off-by: default avatarTimo Teräs <timo.teras@iki.f>
      Cc: Sachin Kamat <sachin.kamat@linaro.org>
      Cc: Raphael Assenat <raph@8d.com>
      Cc: Trent Piepho <tpiepho@freescale.com>
      Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
      Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
      Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
      Acked-by: default avatarJingoo Han <jg1.han@samsung.com>
      Signed-off-by: default avatarBryan Wu <cooloney@gmail.com>
    • Linus Torvalds's avatar
      Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux · e748a385
      Linus Torvalds authored
      Pull i2c bugfixes from Wolfram Sang:
       "These should have been in rc2 but I missed it due to working on devm
        longer than expected.
        There is one ID addition, since we are touching the driver anyhow.
        And the feature bit documentation is one outcome of a debug session
        and will make it easier for users to work around problems.  The rest
        is typical driver bugfixes."
      * 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
        i2c: suppress lockdep warning on delete_device
        i2c: mv64xxx: work around signals causing I2C transactions to be aborted
        i2c: i801: Document feature bits in modinfo
        i2c: designware: add Intel BayTrail ACPI ID
        i2c: designware: always clear interrupts before enabling them
        i2c: designware: fix RX FIFO overrun
    • Linus Torvalds's avatar
      Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux · c4ad180f
      Linus Torvalds authored
      Pull s390 update from Martin Schwidefsky:
       "An additional sysfs attribute for channel paths and a couple of bux
      * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux:
        s390/pgtable: fix ipte notify bit
        s390/xpram: mark xpram as non-rotational
        s390/smp: fix cpu re-scan vs. cpu state
        s390/cio: add channel ID sysfs attribute
        s390/ftrace: fix mcount adjustment
        s390: fix gmap_ipte_notifier vs. software dirty pages
        s390: disable pfmf for clear page instruction
        s390/disassembler: prevent endless loop in print_fn_code()
        s390: remove non existent reference to GENERIC_KERNEL_THREAD
    • Stephen Boyd's avatar
      ARM: smp: Drop RCU_NONIDLE usage in cpu_die() · aa033810
      Stephen Boyd authored
      Before f7b861b7 ("arm: Use generic idle loop") ARM would kill the
      CPU within the rcu idle section.  Now that the rcu_idle_enter()/exit()
      pair have been pushed lower down in the idle loop this is no longer true
      and so using RCU_NONIDLE here is no longer necessary and also harmful
      because RCU is not actually idle at this point.
      Cc: Russell King <linux@arm.linux.org.uk>
      Acked-by: default avatarPaul E. McKenney <paulmck@linux.vnet.ibm.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
    • Linus Torvalds's avatar
      Merge branch 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux · 0ddaa974
      Linus Torvalds authored
      Pull radeon sun/hainan support from  Dave Airlie:
       "Since I know its outside the merge window, but since this is new hw I
        thought I'd try and provoke the new hw exception, it just fills in the
        blanks in the driver for the new AMD sun and hainan chipsets."
      * 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux:
        drm/radeon: add Hainan pci ids
        drm/radeon: add golden register settings for Hainan (v2)
        drm/radeon: sun/hainan chips do not have UVD (v2)
        drm/radeon: track which asics have UVD
        drm/radeon: radeon-asic updates for Hainan
        drm/radeon: fill in ucode loading support for Hainan
        drm/radeon: don't touch DCE or VGA regs on Hainan (v3)
        drm/radeon: fill in GPU init for Hainan (v2)
        drm/radeon: add chip family for Hainan
    • Linus Torvalds's avatar
      Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux · 007b703b
      Linus Torvalds authored
      Pull DRM fixes from Dave Airlie:
       "This is just a set of nouveau and radeon fixes, the nouveau ones fix
        some suspend/resume regressions since use of copy engines and some
        fixes for Z compression on some newer chipsets."
      * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
        drm/radeon/dce2: use 10khz units for audio dto calculation
        drm/radeon: Fix VRAM size calculation for VRAM >= 4GB
        drm/radeon: Remove superfluous variable
        drm/nouveau: ensure channels are stopped before saving fences for suspend
        drm/nv50/fifo: prevent races between clients updating playlists
        drm/nvc0/fifo: prevent CHAN_TABLE_ERROR:CHANNEL_PENDING on fifo fini
        drm/nvc0/fifo: prevent races between clients updating playlists
        drm/nve0/fifo: prevent races between clients updating playlists
        drm/nve0/ltcg: poke the partition count into yet another register
        drm/nvc0/ltcg: fix handling of disabled partitions
        drm/nvc0/ce: disable ce1 on a number of chipsets
        drm/nouveau/bios: fix thinko in ZM_MASK_ADD opcode
        drm/nouveau: fix build with nv50->nvc0
    • Jon Medhurst's avatar
      ARM: Enable selection of SMP operations at boot time · b382b940
      Jon Medhurst authored
      Add a new 'smp_init' hook to machine_desc so platforms can specify a
      function to be used to setup smp ops instead of having a statically
      defined value.  The hook must return true when smp_ops are initialized.
      If false the static mdesc->smp_ops will be used by default.
      Add the definition of "bool" by including the linux/types.h file to
      asm/mach/arch.h and make it self-contained.
      Signed-off-by: default avatarJon Medhurst <tixy@linaro.org>
      Signed-off-by: default avatarNicolas Pitre <nicolas.pitre@linaro.org>
      Signed-off-by: default avatarStefano Stabellini <stefano.stabellini@eu.citrix.com>
      Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
      Reviewed-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
    • Stefano Stabellini's avatar
      arm: introduce psci_smp_ops · 05774088
      Stefano Stabellini authored
      Rename virt_smp_ops to psci_smp_ops and move them to arch/arm/kernel/psci_smp.c.
      Remove mach-virt/platsmp.c, now unused.
      Compile psci_smp if CONFIG_ARM_PSCI and CONFIG_SMP.
      Add a cpu_die smp_op based on psci_ops.cpu_off.
      Initialize PSCI before setting smp_ops in setup_arch.
      If PSCI is available on the platform, prefer psci_smp_ops over the
      platform smp_ops.
      Signed-off-by: default avatarStefano Stabellini <stefano.stabellini@eu.citrix.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      CC: arnd@arndb.de
      CC: marc.zyngier@arm.com
      CC: linux@arm.linux.org.uk
      CC: nico@linaro.org
      CC: rob.herring@calxeda.com
  5. 20 May, 2013 10 commits