Commit f5c122da authored by Kevin Hilman's avatar Kevin Hilman
Browse files

davinci: add arch_ioremap() which uses existing static mappings



Add arch-specific ioremap() which uses any existing static mappings in
place of doing a new mapping.  From now on, drivers should always use
ioremap() instead of IO_ADDRESS().

In addition, remove the davinci_[read|write]* macros in favor of using
ioremap.

Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent c5b736d0
......@@ -36,6 +36,9 @@
#include <mach/common.h>
#include <mach/i2c.h>
#define DAVINCI_CFC_ATA_BASE 0x01C66000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
/* other misc. init functions */
void __init davinci_psc_init(void);
void __init davinci_irq_init(void);
......@@ -422,7 +425,6 @@ static __init void davinci_evm_init(void)
static __init void davinci_evm_irq_init(void)
{
davinci_init_common_hw();
davinci_irq_init();
}
......
......@@ -22,6 +22,8 @@
#include <mach/i2c.h>
#include <mach/irqs.h>
#define DAVINCI_I2C_BASE 0x01C21000
static struct resource i2c_resources[] = {
{
.start = DAVINCI_I2C_BASE,
......
......@@ -15,7 +15,7 @@
#include <linux/init.h>
#include <linux/io.h>
#define JTAG_ID_BASE 0x01c40028
#define JTAG_ID_BASE IO_ADDRESS(0x01c40028)
static unsigned int davinci_revision;
......@@ -58,7 +58,7 @@ static u16 __init davinci_get_part_no(void)
{
u32 dev_id, part_no;
dev_id = davinci_readl(JTAG_ID_BASE);
dev_id = __raw_readl(JTAG_ID_BASE);
part_no = ((dev_id >> 12) & 0xffff);
......@@ -72,7 +72,7 @@ static u8 __init davinci_get_variant(void)
{
u32 variant;
variant = davinci_readl(JTAG_ID_BASE);
variant = __raw_readl(JTAG_ID_BASE);
variant = (variant >> 28) & 0xf;
......
......@@ -15,9 +15,11 @@
#include <linux/io.h>
#include <asm-generic/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#define DAVINCI_GPIO_BASE 0x01C67000
/*
* basic gpio routines
*
......
/*
* Common hardware definitions
* Hardware definitions common to all DaVinci family processors
*
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
* Author: Kevin Hilman, Deep Root Systems, LLC
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -12,41 +12,16 @@
#define __ASM_ARCH_HARDWARE_H
/*
* Base register addresses
* Before you add anything to ths file:
*
* This header is for defines common to ALL DaVinci family chips.
* Anything that is chip specific should go in <chipname>.h,
* and the chip/board init code should then explicitly include
* <chipname>.h
*/
#define DAVINCI_DMA_3PCC_BASE (0x01C00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01C10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01C10400)
#define DAVINCI_I2C_BASE (0x01C21000)
#define DAVINCI_PWM0_BASE (0x01C22000)
#define DAVINCI_PWM1_BASE (0x01C22400)
#define DAVINCI_PWM2_BASE (0x01C22800)
#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
#define DAVINCI_IEEE1394_BASE (0x01C60000)
#define DAVINCI_USB_OTG_BASE (0x01C64000)
#define DAVINCI_CFC_ATA_BASE (0x01C66000)
#define DAVINCI_SPI_BASE (0x01C66800)
#define DAVINCI_GPIO_BASE (0x01C67000)
#define DAVINCI_UHPI_BASE (0x01C67800)
#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
#define DAVINCI_IMCOP_BASE (0x01CC0000)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
#define DAVINCI_VLYNQ_BASE (0x01E01000)
#define DAVINCI_MCBSP_BASE (0x01E02000)
#define DAVINCI_MMC_SD_BASE (0x01E10000)
#define DAVINCI_MS_BASE (0x01E20000)
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000
/* System control register offsets */
#define DM64XX_VDD3P3V_PWDN 0x48
#endif /* __ASM_ARCH_HARDWARE_H */
......@@ -40,22 +40,12 @@
#else
#define IOMEM(x) ((void __force __iomem *)(x))
/*
* Functions to access the DaVinci IO region
*
* NOTE: - Use davinci_read/write[bwl] for physical register addresses
* - Use __raw_read/write[bwl]() for virtual register addresses
* - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
* - DO NOT use hardcoded virtual addresses to allow changing the
* IO address space again if needed
*/
#define davinci_readb(a) __raw_readb(IO_ADDRESS(a))
#define davinci_readw(a) __raw_readw(IO_ADDRESS(a))
#define davinci_readl(a) __raw_readl(IO_ADDRESS(a))
#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
#define __arch_iounmap(v) davinci_iounmap(v)
#define davinci_writeb(v, a) __raw_writeb(v, IO_ADDRESS(a))
#define davinci_writew(v, a) __raw_writew(v, IO_ADDRESS(a))
#define davinci_writel(v, a) __raw_writel(v, IO_ADDRESS(a))
void __iomem *davinci_ioremap(unsigned long phys, size_t size,
unsigned int type);
void davinci_iounmap(volatile void __iomem *addr);
#endif /* __ASSEMBLER__ */
#endif /* __ASM_ARCH_IO_H */
......@@ -51,6 +51,26 @@ void __init davinci_map_common_io(void)
davinci_check_revision();
}
void __init davinci_init_common_hw(void)
#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst)))
/*
* Intercept ioremap() requests for addresses in our fixed mapping regions.
*/
void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
{
if (BETWEEN(p, IO_PHYS, IO_SIZE))
return XLATE(p, IO_PHYS, IO_VIRT);
return __arm_ioremap(p, size, type);
}
EXPORT_SYMBOL(davinci_ioremap);
void davinci_iounmap(volatile void __iomem *addr)
{
unsigned long virt = (unsigned long)addr;
if (virt >= VMALLOC_START && virt < VMALLOC_END)
__iounmap(addr);
}
EXPORT_SYMBOL(davinci_iounmap);
......@@ -40,14 +40,16 @@
#define IRQ_INTPRI0_REG_OFFSET 0x0030
#define IRQ_INTPRI7_REG_OFFSET 0x004C
#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
static inline unsigned int davinci_irq_readl(int offset)
{
return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
return __raw_readl(INTC_BASE + offset);
}
static inline void davinci_irq_writel(unsigned long value, int offset)
{
davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
__raw_writel(value, INTC_BASE + offset);
}
/* Disable interrupt */
......
......@@ -23,6 +23,7 @@ static DEFINE_SPINLOCK(mux_lock);
void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
{
void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
u32 pinmux, muxreg = PINMUX0;
if (mux >= DAVINCI_MUX_LEVEL2) {
......@@ -31,11 +32,11 @@ void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
}
spin_lock(&mux_lock);
pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
pinmux = __raw_readl(base + muxreg);
if (enable)
pinmux |= (1 << mux);
else
pinmux &= ~(1 << mux);
davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
__raw_writel(pinmux, base + muxreg);
spin_unlock(&mux_lock);
}
......@@ -28,6 +28,8 @@
#include <mach/psc.h>
#include <mach/mux.h>
#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
/* PSC register offsets */
#define EPCPR 0x070
#define PTCMD 0x120
......
......@@ -16,6 +16,9 @@
#include <linux/clockchips.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/device.h>
#include <mach/hardware.h>
#include <asm/system.h>
......@@ -24,6 +27,8 @@
#include <asm/mach/time.h>
#include <asm/errno.h>
#include <mach/io.h>
#include <mach/cputype.h>
#include "clock.h"
static struct clock_event_device clockevent_davinci;
......@@ -99,9 +104,9 @@ struct timer_s {
unsigned int id;
unsigned long period;
unsigned long opts;
unsigned long reg_base;
unsigned long tim_reg;
unsigned long prd_reg;
void __iomem *base;
unsigned long tim_off;
unsigned long prd_off;
unsigned long enamode_shift;
struct irqaction irqaction;
};
......@@ -114,15 +119,15 @@ static struct timer_s timers[];
static int timer32_config(struct timer_s *t)
{
u32 tcr = davinci_readl(t->reg_base + TCR);
u32 tcr = __raw_readl(t->base + TCR);
/* disable timer */
tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
davinci_writel(tcr, t->reg_base + TCR);
__raw_writel(tcr, t->base + TCR);
/* reset counter to zero, set new period */
davinci_writel(0, t->tim_reg);
davinci_writel(t->period, t->prd_reg);
__raw_writel(0, t->base + t->tim_off);
__raw_writel(t->period, t->base + t->prd_off);
/* Set enable mode */
if (t->opts & TIMER_OPTS_ONESHOT) {
......@@ -131,13 +136,13 @@ static int timer32_config(struct timer_s *t)
tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
}
davinci_writel(tcr, t->reg_base + TCR);
__raw_writel(tcr, t->base + TCR);
return 0;
}
static inline u32 timer32_read(struct timer_s *t)
{
return davinci_readl(t->tim_reg);
return __raw_readl(t->base + t->tim_off);
}
static irqreturn_t timer_interrupt(int irq, void *dev_id)
......@@ -176,51 +181,54 @@ static struct timer_s timers[] = {
static void __init timer_init(void)
{
u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
int i;
/* Global init of each 64-bit timer as a whole */
for(i=0; i<2; i++) {
u32 tgcr, base = bases[i];
u32 tgcr;
void __iomem *base = IO_ADDRESS(phys_bases[i]);
/* Disabled, Internal clock source */
davinci_writel(0, base + TCR);
__raw_writel(0, base + TCR);
/* reset both timers, no pre-scaler for timer34 */
tgcr = 0;
davinci_writel(tgcr, base + TGCR);
__raw_writel(tgcr, base + TGCR);
/* Set both timers to unchained 32-bit */
tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
davinci_writel(tgcr, base + TGCR);
__raw_writel(tgcr, base + TGCR);
/* Unreset timers */
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
davinci_writel(tgcr, base + TGCR);
__raw_writel(tgcr, base + TGCR);
/* Init both counters to zero */
davinci_writel(0, base + TIM12);
davinci_writel(0, base + TIM34);
__raw_writel(0, base + TIM12);
__raw_writel(0, base + TIM34);
}
/* Init of each timer as a 32-bit timer */
for (i=0; i< ARRAY_SIZE(timers); i++) {
struct timer_s *t = &timers[i];
u32 phys_base;
if (t->name) {
t->id = i;
t->reg_base = (IS_TIMER1(t->id) ?
phys_base = (IS_TIMER1(t->id) ?
DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
t->base = IO_ADDRESS(phys_base);
if (IS_TIMER_BOT(t->id)) {
t->enamode_shift = 6;
t->tim_reg = t->reg_base + TIM12;
t->prd_reg = t->reg_base + PRD12;
t->tim_off = TIM12;
t->prd_off = PRD12;
} else {
t->enamode_shift = 22;
t->tim_reg = t->reg_base + TIM34;
t->prd_reg = t->reg_base + PRD34;
t->tim_off = TIM34;
t->prd_off = PRD34;
}
/* Register interrupt */
......@@ -333,42 +341,43 @@ struct sys_timer davinci_timer = {
/* reset board using watchdog timer */
void davinci_watchdog_reset(void) {
u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE;
u32 tgcr, wdtcr;
void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
/* disable, internal clock source */
davinci_writel(0, base + TCR);
__raw_writel(0, base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
tgcr = 0;
davinci_writel(tgcr, base + TCR);
__raw_writel(tgcr, base + TCR);
tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
davinci_writel(tgcr, base + TCR);
__raw_writel(tgcr, base + TCR);
/* clear counter and period regs */
davinci_writel(0, base + TIM12);
davinci_writel(0, base + TIM34);
davinci_writel(0, base + PRD12);
davinci_writel(0, base + PRD34);
__raw_writel(0, base + TIM12);
__raw_writel(0, base + TIM34);
__raw_writel(0, base + PRD12);
__raw_writel(0, base + PRD34);
/* enable */
wdtcr = davinci_readl(base + WDTCR);
wdtcr = __raw_readl(base + WDTCR);
wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
davinci_writel(wdtcr, base + WDTCR);
__raw_writel(wdtcr, base + WDTCR);
/* put watchdog in pre-active state */
wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
davinci_writel(wdtcr, base + WDTCR);
__raw_writel(wdtcr, base + WDTCR);
/* put watchdog in active state */
wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
davinci_writel(wdtcr, base + WDTCR);
__raw_writel(wdtcr, base + WDTCR);
/* write an invalid value to the WDKEY field to trigger
* a watchdog reset */
wdtcr = 0x00004000;
davinci_writel(wdtcr, base + WDTCR);
__raw_writel(wdtcr, base + WDTCR);
}
......@@ -14,6 +14,8 @@
#include <mach/hardware.h>
#include <mach/irqs.h>
#define DAVINCI_USB_OTG_BASE 0x01C64000
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
static struct musb_hdrc_eps_bits musb_eps[] = {
{ "ep1_tx", 8, },
......
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