Skip to content
  • Suzuki Poulose's avatar
    arm64: cpufeature: Fix handling of CTR_EL0.IDC field · 1602df02
    Suzuki Poulose authored and Catalin Marinas's avatar Catalin Marinas committed
    CTR_EL0.IDC reports the data cache clean requirements for instruction
    to data coherence. However, if the field is 0, we need to check the
    CLIDR_EL1 fields to detect the status of the feature. Currently we
    don't do this and generate a warning with tainting the kernel, when
    there is a mismatch in the field among the CPUs. Also the userspace
    doesn't have a reliable way to check the CLIDR_EL1 register to check
    the status.
    This patch fixes the problem by checking the CLIDR_EL1 fields, when
    (CTR_EL0.IDC == 0) and updates the kernel's copy of the CTR_EL0 for
    the CPU with the actual status of the feature. This would allow the
    sanity check infrastructure to do the proper checking of the fields
    and also allow the CTR_EL0 emulation code to supply the real status
    of the feature.
    Now, if a CPU has raw CTR_EL0.IDC == 0 and effective IDC == 1 (with
    overall system wide IDC == 1), we need to expose the real value to
    the user. So, we trap CTR_EL0 access on the CPU which reports incorrect
    Fixes: commit 6ae4b6e0
     ("arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC")
    Cc: Shanker Donthineni <>
    Cc: Philip Elcan <>
    Cc: Will Deacon <>
    Cc: Mark Rutland <>
    Signed-off-by: default avatarSuzuki K Poulose <>
    Signed-off-by: default avatarCatalin Marinas <>