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    arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size) · 1f85b42a
    Catalin Marinas authored
    Commit 97303480
     ("arm64: Increase the max granular size") increased
    the cache line size to 128 to match Cavium ThunderX, apparently for some
    performance benefit which could not be confirmed. This change, however,
    has an impact on the network packets allocation in certain
    circumstances, requiring slightly over a 4K page with a significant
    performance degradation.
    This patch reverts L1_CACHE_SHIFT back to 6 (64-byte cache line) while
    keeping ARCH_DMA_MINALIGN at 128. The cache_line_size() function was
    changed to default to ARCH_DMA_MINALIGN in the absence of a meaningful
    CTR_EL0.CWG bit field.
    In addition, if a system with ARCH_DMA_MINALIGN < CTR_EL0.CWG is
    detected, the kernel will force swiotlb bounce buffering for all
    non-coherent devices since DMA cache maintenance on sub-CWG ranges is
    not safe, leading to data corruption.
    Cc: Tirumalesh Chalamarla <>
    Cc: Timur Tabi <>
    Cc: Florian Fainelli <>
    Acked-by: default avatarRobin Murphy <>
    Signed-off-by: default avatarCatalin Marinas <>
    Signed-off-by: default avatarWill Deacon <>