Skip to content
  • Suzuki Poulose's avatar
    arm64: Fix mismatched cache line size detection · 4c4a39dd
    Suzuki Poulose authored
    If there is a mismatch in the I/D min line size, we must
    always use the system wide safe value both in applications
    and in the kernel, while performing cache operations. However,
    we have been checking more bits than just the min line sizes,
    which triggers false negatives. We may need to trap the user
    accesses in such cases, but not necessarily patch the kernel.
    This patch fixes the check to do the right thing as advertised.
    A new capability will be added to check mismatches in other
    fields and ensure we trap the CTR accesses.
    Fixes: be68a8aa
     ("arm64: cpufeature: Fix CTR_EL0 field definitions")
    Cc: <>
    Cc: Mark Rutland <>
    Cc: Catalin Marinas <>
    Reported-by: default avatarWill Deacon <>
    Signed-off-by: default avatarSuzuki K Poulose <>
    Signed-off-by: default avatarWill Deacon <>