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  • Vincenzo Frascino's avatar
    arm64: mte: Enable async tag check fault · 8c24f249
    Vincenzo Frascino authored
    MTE provides a mode that asynchronously updates the TFSR_EL1 register
    when a tag check exception is detected.
    To take advantage of this mode the kernel has to verify the status of
    the register at:
      1. Context switching
      2. Return to user/EL0 (Not required in entry from EL0 since the kernel
      did not run)
      3. Kernel entry from EL1
      4. Kernel exit to EL1
    If the register is non-zero a trace is reported.
    Add the required features for EL1 detection and reporting.
    Note: ITFSB bit is set in the SCTLR_EL1 register hence it guaranties that
    the indirect writes to TFSR_EL1 are synchronized at exception entry to
    EL1. On the context switch path the synchronization is guarantied by the
    dsb() in __switch_to().
    The dsb(nsh) in mte_check_tfsr_exit() is provisional pending
    confirmation by the architects.
    Cc: Catalin Marinas <>
    Cc: Will Deacon <>
    Reviewed-by: default avatarCatalin Marinas <>
    Acked-by: default avatarAndrey Konovalov <>
    Signed-off-by: default avatarVincenzo Frascino <>