Modified defconfig and dtses' to sync with latest mobile like gem5 baseline.
Updated gem5 cpufreq drivers to avoid registering when dvfs handler is
disabled in the gem5 hardware.

The energy controller enables DVFS (dynamic voltage and frequency
scaling support) of gem5 for up to 32 independent domains (or clusters).
The changes are modelled somewhat after the VExpress SPC component, but
are specific to gem5.

This fixes a problem with dc zva/WriteInvalidate testing on v7. The
The system has coherent I/O and the kernel needs to know this.

What would happen is the IO cache would hold DMA descriptor information
in Exclusive state and the core would send uncacheable requests that
effectively bypassed the coherence.  The IO device would then act on
incoherent data.

This change in conjunction with changeset 2258 in gem5 (patch queue)
makes the architecture timer work.

Signed-off-by: Rene de Jong <rene.dejong@arm.com>
Signed-off-by: Chris Emmons <chris.emmons@arm.com>

Add config options that fix MSI-X, coherent IO, etc.

Signed-off-by: Geoffrey Blake <geobla01@arm.com>
Signed-off-by: Chris Emmons <chris.emmons@arm.com>

The gem5 NVMe device adheres to that; but the io.h functions do not. This
has as consequence that the reading of those registers get split up in two
transactions of 32 bits. This is not supported by the NVMe device.

According to the NVMe spec, certain registers must be read as 64 bit values.

This patch adds a 4K resolution option to the HDLcd controller
which the real hardware is not capable of. This mode will be useful
for future-looking studies. The default resolution is unchanged;
you will need to update the dts file to enable 4K (see the new
comment in the dts file HDLcd controller section).  You will also
want to change the HDLcd oscillator frequency in RealView.py to get
the frame rate you want as writing of the Versatile Express
oscillator registers currently doesn't have any effect on the gem5
model.  Tested with Android Jelly Bean.

Signed-off-by: Christopher Daniel Emmons <chris.emmons@arm.com>

Signed-off-by: Christopher Daniel Emmons <chris.emmons@arm.com>

UFS support is compiled into gem5 kernels by default.  However, it
is still disabled in the dts file by default.  Uncommenting it in
the dts *should* make it work with an appropriately-configured
system.

Signed-off-by: Christopher Daniel Emmons <chris.emmons@arm.com>

Signed-off-by: Christopher Daniel Emmons <chris.emmons@arm.com>

Conflicting files:
arch/arm/mach-exynos/headsmp.S

workaround

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>

Append AHCI_HFLAG_NO_FBS to force turning off FBS flag.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

ARM Performance Monitor Units are available on the hip04,
add the support in the dtsi.

Simply tested with perf.

Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>

This reverts commit f1a34227.

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

./scripts/kconfig/merge_config.sh arch/arm/configs/multi_v7_defconfig linaro/configs/hip04.conf

The above command is used to produce the configuration file to bring up
ubuntu.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

test:
ifconfig eth1 192.168.1.99; ping 192.168.1.10

by default pc ethernet is 100M, also can work
Can be change via command:
host:
sudo ethtool eth0
sudo ethtool -s eth0 duplex full speed 1000

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

Add mdio interface, and reuse phy drivers/net/phy/marvell.c

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

test:
ifconfig eth0 192.168.10.1; ping 192.168.10.6 (host)

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

part1: add frame for specific sata vsemiphy init.

Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>

Add sata device node for hisi hip04 soc.

Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>

The hip04 SoC of hisilicon has an AHCI compliant SATA controller.
This patch adds the compatible string, and the controller is compliant
with the ahci 1.3 and sata 3.0 specification.

ISSUE: The hardware has defective designs.

Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Enable SMP to support 4 cores. 16 cores could be supported at most.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>